`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:10:26 07/09/2015
// Design Name:   Pipeline
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/PipeTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Pipeline
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module PipeTest;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire [31:0] salida;
	wire [31:0] salidaInst;
	wire [31:0] salidaL1;
	wire mux;
	wire otracosa;

	// Instantiate the Unit Under Test (UUT)
	Pipeline uut (
		.clk(clk), 
		.reset(reset), 
		.salida(salida),
		.salidaInst(salidaInst),
		.salidaL1(salidaL1),
		.mux(mux),
		.otracosa(otracosa)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;
		#10;
		reset = 0;
		// Add stimulus here

	end
	
 always begin
#1; clk = ~clk; end

endmodule

